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SMIC and CADENCE Deliver New Analog Mixed-Signal Reference Flow to Speed Fabless Chip Design

13 Apr 2006

Speed Fabless Chip Design
 
Shanghai  [2006-04-13]

New Jointly Designed Reference Flow Improves Designer Productivity for Consumer, Networking and Wireless Markets

SAN JOSE, Calif. and SHANGHAI, China - April 13, 2006 - Cadence Design Systems, Inc. (NASDAQ: CDNS) and Semiconductor Manufacturing International Corporation ("SMIC", NYSE: SMI; SEHK: 0981.HK) today announced that the companies have jointly developed an analog mixed-signal (AMS) reference flow to address the needs of designers developing ICs for the consumer, networking and wireless markets.

The block-level reference flow is based on SMIC's 0.18um multi-mode, radio-frequency process design kit (PDK) and the Cadence® Virtuoso® custom design platform and Design for Manufacturing (DFM) technologies. The flow has been proven through silicon and package validation of a sample analog-to-digital converter (ADC) design. The flow improves designer productivity by providing a reference design environment, baseline flow and an example design demonstrating how designers can use SMIC process technology and the Cadence Virtuoso platform.

"Our collaboration with Cadence helps to drive our goal of continuing to enable the Chinese semiconductor market," said Paul Ouyang, vice president of Design Services, SMIC. "As a leader in analog mixed-signal design solutions, Cadence has provided its unique technology and expertise to create this reference flow. This solution will help to facilitate analog mixed-signal design for the growing consumer, networking and wireless markets."

"Cadence and SMIC aim to continue collaborating on improving designers' productivity by focusing on mainstream and advanced process technologies," said Mike McAweeney, vice president of business development of Industry Alliances at Cadence. "Cadence has a strong worldwide foundry access team that works with leading foundries to develop PDKs and reference flows that enable customers to speed up product development cycles and reduce design failure risks. The AMS reference flow is a result of the continuing efforts of Cadence and SMIC to ensure customer success through collaboration."

The SMIC-Cadence analog mixed-signal reference flow, based on OpenAccess 2.2, the industry open database standard, provides designers an optimized and predictable schematic-to-GDSII flow. The flow provides a starting point for design teams creating SoCs or putting together a flow of their own. The flow incorporates several Cadence technologies, including Virtuoso Spectre® Circuit Simulator, Virtuoso UltraSim Full-chip Simulator, Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Virtuoso Specification-driven Environment, Virtuoso Chip Assembly Router, Virtuoso XL Layout Editor, Assura™ Design Rule Checker (DRC) / Layout vs. Schematic (LVS) Verifier and Cadence QRC Extraction.

Availability
The SMIC and Cadence AMS reference flow kit is available to SMIC customers who may request the reference flow by contacting SMIC's Design Services at design_services@3dsentson.com.


About SMIC
Semiconductor Manufacturing International Corporation, ("SMIC", NYSE: SMI and HKSE: 0.981.HK), headquartered in Shanghai, China, is an international company and one of the leading semiconductor foundries in the world, providing integrated circuit (IC) manufacturing at 0.35um to 90nm and finer line technologies to customers worldwide. Established in 2000, SMIC has four 8-inch wafer fabrication facilities in volume production in Shanghai and Tianjin. In the first quarter of 2005, SMIC commenced commercial production at its 12-inch wafer fabrication facility in Beijing, the first 12-inch fab in China. SMIC also maintains customer service and marketing offices in the U.S., Europe, and Japan, and a representative office in Hong Kong. SMIC's pool of talents includes over 2,500 semiconductor industry experts and technical staff. SMIC has achieved ISO9001, ISO/TS16949, OHSAS18001, TL9000, BS7799 and ISO14001 certifications. For additional information, please visit http://www.3dsentson.com.

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo, Virtuoso, and Spectre are registered trademarks, and Assura is a trademark, of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Safe Harbor Statements
(Under the U.S. Private Securities Litigation Reform Act of 1995)
Certain statements contained in this press release, may be viewed as "forward-looking statements" within the meaning of Section 27A of the U.S. Securities Act of 1933, as amended, and Section 21E of the U.S. Securities Exchange Act of 1934, as amended. Such forward-looking statements involve known and unknown risks, uncertainties and other factors, which may cause actual events, and/or the actual performance, financial condition or results of operations of SMIC to be materially different from any future performance, financial condition or results of operations implied by such forward-looking statements. Further information regarding these risks, uncertainties and other factors is included in the Company's annual report on Form 20-F filed with the U.S. Securities and Exchange Commission (the "SEC") on June 28, 2005 and such other documents that SMIC may file with the SEC or The Stock Exchange of Hong Kong Limited from time to time.
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