Press Releases
SMIC and Virage Logic Expand Partnership to Offer Virage Logic's IP on SMIC's 65nm LL Process
SMIC's 65nm LL Process
Shanghai [2010-05-24]
Partnership Brings SiWare Memory, SiWare Logic, SiPro MIPI and Intelli DDR Best-in-Class IP to SMIC's 65nm LL Process
FREMONT, Calif. and SHANGHAI, China – May 24, 2010 – Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP partner, and Semiconductor Manufacturing International Corporation (SMIC; NYSE: SMI and SEHK: 0981.HK), the leading foundry in China, today announced the expansion of their longstanding partnership to include the 65-nanometer (nm) low-leakage (LL) process technology. Under the terms of the agreement, System-on-Chip (SoC) designers will have access to Virage Logic’s SiWare Memory compilers, SiWare Logic libraries, SiPro MIPIand Intelli DDR IP on SMIC’s 65nm LL process. This joint agreement is part of Virage Logic's strategy to expand its business through industry leading foundries and highlights SMIC's commitment to provide a complete IP solution for its customers.
“As the premier foundry in China, our expanded partnership with Virage Logic will enable SMIC to offer the industry leading semiconductor IP on our 65nm LL process to meet the needs of not only the Chinese system-on-chip (SoC) developers but the global semiconductor market,.” said Chris Chi, Senior Vice President and Chief Business Officer of SMIC. “Currently we have a number of customers with projects leveraging SMIC’s 65nm LL node with the extended Virage Logic IP offering. As SMIC’s business continues to expand, we look forward to growing our synergistic relationship with Virage Logic to meet the increasing market demand.”
“We are pleased to expand our partnership with SMIC to the 65nm LL process. With this comprehensive offering of Virage Logic’s industry leading IP, customers will be able to select SMIC as their primary source for their 65nm manufacturing requirements,” said Brani Buric, executive vice president of marketing and sales for Virage Logic. “SMIC recognizes the strategic benefits of making our SiWare Memory and SiWare Logic IP available to end users free of charge as part of a foundry-sponsored IP offering. Our SiPro MIPI and Intelli DDR standards-based high-speed interface IP offering also provides a proven solution so now designers everywhere have the option to select the best-in-class IP for their 65nm LL based designs.”
About Virage Logic’s SiPro MIPI IP
The SiPro MIPI DSI (display serial interface), CSI (camera serial interface) controllers and D-PHY IP are optimized for power, area, yield and performance. The SiPro MIPI IP was system-validated with device ICs to provide seamless interoperability for evolving mobile electronics applications interfacing cameras and displays. The SiPro MIPI IP solutions, used in a host of SoC mobile applications, are production-proven on the advanced 65nm LP process node and available on the 40nm LP process node.
About Virage Logic’s Intelli? DDR Interface IP Solution
The Intelli DDR memory interface product offers the highest performance, lowest latency intelligent memory controllers for DDR1, DDR2, and DDR3; the lowest power, highest bandwidth Mobile SDR, Mobile DDR, Low Power DDR (LPDDR) and LPDDR2 memory controllers; high-speed, full digital DDR SDRAM PHY+DLL solutions and state of the art highly configurable DDR IOs. The Intelli PHY+DLL companion for the Intelli DDR memory interface products is an all-digital DDR PHY+DLL hard macro GDSII solution optimized for high performance and low power applications. The all digital PHY+DLL consumes up to 25% lower power and is up to 20% smaller in area to comparable analog solutions.
About Virage Logic’s SiWare Memory and SiWare Logic Products
The SiWare product line, first introduced in October 2007 for the 65nm process and now in use by more than 40 customers on the 40nm process, has been proven to address the increasingly complex design requirements that are placed on physical IP at advanced processes. The power-optimized memories for advanced processes minimize both static and dynamic power consumption and provide optimal yields. SiWare High-Density memory compilers are optimized to generate memories with minimum area. SiWare High-Speed memory compilers are designed to help designers achieve the most aggressive critical path requirements. Compile-time options for process threshold variants, power saving modes, read and write margin extensions, ultra-low voltage operation, and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements.
All SiWare memories are fully supported by Virage Logic's STAR Memory System, the company's flagship embedded memory test and repair system that may be used with Virage Logic memories as well as with other commercially available or internally developed memories. For repair purposes, the STAR Memory System deploys foundry-developed eFuse for repair signature storage. The STAR Memory System employs test algorithms tailored for advanced processes for higher product reliability and accelerated time-to-yield.
The SiWare Logic product line offers yield-optimized High-Speed and High-Density standard cells that are available in multi-channel configurations and multiple threshold variants. These libraries contain over 1,100 base library cells with multiple cell variants and drive strengths to quickly achieve timing closure without wasting area or power. The cells are hand crafted for maximum performance and density.
Virage Logic’s logic libraries maximize yield by adhering to restrictive design rules and multiple contacts for the highest manufacturability and robust electro-migration standards for reliability. Local variations are minimized with uniform layouts, use of non-minimum sized devices, and are accurately characterized in foundry-specified extraction environments that reflect DFM effects such as Well Proximity Effect (WPE) and diffusion spacing with neighboring circuits.
Availability
Virage Logic’s SiWare Memory and SiWare Logic products will be available in Q3 2010. Virage Logic will license these products directly to end customers under its foundry sponsored IP program.
Virage Logic’s SiPro MIPI and Intelli DDR interface IP will be available beginning in Q3 2010
About Virage Logic
Virage Logic is a leading provider of semiconductor intellectual property (IP) for the design of complex integrated circuits. The company's highly differentiated product portfolio includes processor solutions, interface IP solutions, embedded SRAMs and NVMs, embedded test and yield optimization solutions, logic libraries, and memory development software. As the semiconductor industry's trusted IP partner, more than 400 foundry, IDM and fabless customers rely on Virage Logic to achieve higher performance, lower power, higher density and optimal yield, as well as shorten time-to-market and time-to-volume. For further information, visit http://www.viragelogic.com.
Virage Logic Press Contact:
Sabina Burns
Virage Logic Corporation
510-743-8115
sabina.burns@viragelogic.com
About SMIC
Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 981) is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in Mainland China, providing integrated circuit (IC) foundry and technology services at 0.35um to 45nm. Headquartered in Shanghai, China, SMIC has a 300mm wafer fabrication facility (fab) and three 200mm wafer fabs in its Shanghai mega-fab, two 300mm wafer fabs in its Beijing mega-fab, a 200mm wafer fab in Tianjin, a 200mm fab under construction in Shenzhen, and an in-house assembly and testing facility in Chengdu. SMIC also has customer service and marketing offices in the U.S., Europe, and Japan, and a representative office in Hong Kong. In addition, SMIC manages and operates a 200mm wafer fab in Chengdu owned by Cension Semiconductor Manufacturing Corporation and a 300mm wafer fab in Wuhan owned by Wuhan Xinxin Semiconductor Manufacturing Corporation. For more information, please visit http://www.3dsentson.com.
SMIC Contact
SMIC Shanghai
Peter Lin
Public Relations
TEL：+8621 38610000 ext 12349
Email：Peter_LHH@3dsentson.com
SMIC Shanghai
Angela Miao
Public Relations
TEL：+8621 38610000 ext 10088
Email：Angela_Miao@3dsentson.com
SAFE HARBOUR STATEMENTS
(Under the Private Securities Litigation Reform Act of 1995)
This press release contains, in addition to historical information, "forward-looking statements" within the meaning of the "safe harbor" provisions of the U.S. Private Securities Litigation Reform Act of 1995. These forward-looking statements are based on SMIC's current assumptions, expectations and projections about future events. SMIC uses words like "believe," "anticipate," "intend," "estimate," "expect," "project" and similar expressions to identify forward-looking statements, although not all forward-looking statements contain these words. These forward-looking statements involve significant risks, both known and unknown, uncertainties and other factors that may cause SMIC's actual performance, financial condition or results of operations to be materially different from those suggested by the forward-looking statements, including among others risks associated with the current global financial crisis, orders or judgments from pending litigation and financial stability in end markets.
Investors should consider the information contained in SMIC's filings with the U.S. Securities and Exchange Commission (SEC), including its Annual Report on Form 20-F filed with the SEC on June 22, 2009, especially in the "Risk Factors" and "Management's Discussion and Analysis of Financial Condition and Results of Operations" sections, and such other documents that SMIC may file with the SEC or SEHK from time to time, including on Form 6-K. Other unknown or unpredictable factors also could have material adverse effects on SMIC's future results, performance or achievements. In light of these risks, uncertainties, assumptions and factors, the forward-looking events discussed in this press release may not occur. You are cautioned not to place undue reliance on these forward-looking statements, which speak only as of the date stated, or if no date is stated, as of the date of this press release. Except as may be required by law, SMIC undertakes no obligation and does not intend to update any forward-looking statement, whether as a result of new information, future events or otherwise.
All trademarks are the property of their respective owners and are protected herein.
Shanghai [2010-05-24]
Partnership Brings SiWare Memory, SiWare Logic, SiPro MIPI and Intelli DDR Best-in-Class IP to SMIC's 65nm LL Process
FREMONT, Calif. and SHANGHAI, China – May 24, 2010 – Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP partner, and Semiconductor Manufacturing International Corporation (SMIC; NYSE: SMI and SEHK: 0981.HK), the leading foundry in China, today announced the expansion of their longstanding partnership to include the 65-nanometer (nm) low-leakage (LL) process technology. Under the terms of the agreement, System-on-Chip (SoC) designers will have access to Virage Logic’s SiWare Memory compilers, SiWare Logic libraries, SiPro MIPIand Intelli DDR IP on SMIC’s 65nm LL process. This joint agreement is part of Virage Logic's strategy to expand its business through industry leading foundries and highlights SMIC's commitment to provide a complete IP solution for its customers.
“As the premier foundry in China, our expanded partnership with Virage Logic will enable SMIC to offer the industry leading semiconductor IP on our 65nm LL process to meet the needs of not only the Chinese system-on-chip (SoC) developers but the global semiconductor market,.” said Chris Chi, Senior Vice President and Chief Business Officer of SMIC. “Currently we have a number of customers with projects leveraging SMIC’s 65nm LL node with the extended Virage Logic IP offering. As SMIC’s business continues to expand, we look forward to growing our synergistic relationship with Virage Logic to meet the increasing market demand.”
“We are pleased to expand our partnership with SMIC to the 65nm LL process. With this comprehensive offering of Virage Logic’s industry leading IP, customers will be able to select SMIC as their primary source for their 65nm manufacturing requirements,” said Brani Buric, executive vice president of marketing and sales for Virage Logic. “SMIC recognizes the strategic benefits of making our SiWare Memory and SiWare Logic IP available to end users free of charge as part of a foundry-sponsored IP offering. Our SiPro MIPI and Intelli DDR standards-based high-speed interface IP offering also provides a proven solution so now designers everywhere have the option to select the best-in-class IP for their 65nm LL based designs.”
About Virage Logic’s SiPro MIPI IP
The SiPro MIPI DSI (display serial interface), CSI (camera serial interface) controllers and D-PHY IP are optimized for power, area, yield and performance. The SiPro MIPI IP was system-validated with device ICs to provide seamless interoperability for evolving mobile electronics applications interfacing cameras and displays. The SiPro MIPI IP solutions, used in a host of SoC mobile applications, are production-proven on the advanced 65nm LP process node and available on the 40nm LP process node.
About Virage Logic’s Intelli? DDR Interface IP Solution
The Intelli DDR memory interface product offers the highest performance, lowest latency intelligent memory controllers for DDR1, DDR2, and DDR3; the lowest power, highest bandwidth Mobile SDR, Mobile DDR, Low Power DDR (LPDDR) and LPDDR2 memory controllers; high-speed, full digital DDR SDRAM PHY+DLL solutions and state of the art highly configurable DDR IOs. The Intelli PHY+DLL companion for the Intelli DDR memory interface products is an all-digital DDR PHY+DLL hard macro GDSII solution optimized for high performance and low power applications. The all digital PHY+DLL consumes up to 25% lower power and is up to 20% smaller in area to comparable analog solutions.
About Virage Logic’s SiWare Memory and SiWare Logic Products
The SiWare product line, first introduced in October 2007 for the 65nm process and now in use by more than 40 customers on the 40nm process, has been proven to address the increasingly complex design requirements that are placed on physical IP at advanced processes. The power-optimized memories for advanced processes minimize both static and dynamic power consumption and provide optimal yields. SiWare High-Density memory compilers are optimized to generate memories with minimum area. SiWare High-Speed memory compilers are designed to help designers achieve the most aggressive critical path requirements. Compile-time options for process threshold variants, power saving modes, read and write margin extensions, ultra-low voltage operation, and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements.
All SiWare memories are fully supported by Virage Logic's STAR Memory System, the company's flagship embedded memory test and repair system that may be used with Virage Logic memories as well as with other commercially available or internally developed memories. For repair purposes, the STAR Memory System deploys foundry-developed eFuse for repair signature storage. The STAR Memory System employs test algorithms tailored for advanced processes for higher product reliability and accelerated time-to-yield.
The SiWare Logic product line offers yield-optimized High-Speed and High-Density standard cells that are available in multi-channel configurations and multiple threshold variants. These libraries contain over 1,100 base library cells with multiple cell variants and drive strengths to quickly achieve timing closure without wasting area or power. The cells are hand crafted for maximum performance and density.
Virage Logic’s logic libraries maximize yield by adhering to restrictive design rules and multiple contacts for the highest manufacturability and robust electro-migration standards for reliability. Local variations are minimized with uniform layouts, use of non-minimum sized devices, and are accurately characterized in foundry-specified extraction environments that reflect DFM effects such as Well Proximity Effect (WPE) and diffusion spacing with neighboring circuits.
Availability
Virage Logic’s SiWare Memory and SiWare Logic products will be available in Q3 2010. Virage Logic will license these products directly to end customers under its foundry sponsored IP program.
Virage Logic’s SiPro MIPI and Intelli DDR interface IP will be available beginning in Q3 2010
About Virage Logic
Virage Logic is a leading provider of semiconductor intellectual property (IP) for the design of complex integrated circuits. The company's highly differentiated product portfolio includes processor solutions, interface IP solutions, embedded SRAMs and NVMs, embedded test and yield optimization solutions, logic libraries, and memory development software. As the semiconductor industry's trusted IP partner, more than 400 foundry, IDM and fabless customers rely on Virage Logic to achieve higher performance, lower power, higher density and optimal yield, as well as shorten time-to-market and time-to-volume. For further information, visit http://www.viragelogic.com.
Virage Logic Press Contact:
Sabina Burns
Virage Logic Corporation
510-743-8115
sabina.burns@viragelogic.com
About SMIC
Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 981) is one of the leading semiconductor foundries in the world and the largest and most advanced foundry in Mainland China, providing integrated circuit (IC) foundry and technology services at 0.35um to 45nm. Headquartered in Shanghai, China, SMIC has a 300mm wafer fabrication facility (fab) and three 200mm wafer fabs in its Shanghai mega-fab, two 300mm wafer fabs in its Beijing mega-fab, a 200mm wafer fab in Tianjin, a 200mm fab under construction in Shenzhen, and an in-house assembly and testing facility in Chengdu. SMIC also has customer service and marketing offices in the U.S., Europe, and Japan, and a representative office in Hong Kong. In addition, SMIC manages and operates a 200mm wafer fab in Chengdu owned by Cension Semiconductor Manufacturing Corporation and a 300mm wafer fab in Wuhan owned by Wuhan Xinxin Semiconductor Manufacturing Corporation. For more information, please visit http://www.3dsentson.com.
SMIC Contact
SMIC Shanghai
Peter Lin
Public Relations
TEL：+8621 38610000 ext 12349
Email：Peter_LHH@3dsentson.com
SMIC Shanghai
Angela Miao
Public Relations
TEL：+8621 38610000 ext 10088
Email：Angela_Miao@3dsentson.com
SAFE HARBOUR STATEMENTS
(Under the Private Securities Litigation Reform Act of 1995)
This press release contains, in addition to historical information, "forward-looking statements" within the meaning of the "safe harbor" provisions of the U.S. Private Securities Litigation Reform Act of 1995. These forward-looking statements are based on SMIC's current assumptions, expectations and projections about future events. SMIC uses words like "believe," "anticipate," "intend," "estimate," "expect," "project" and similar expressions to identify forward-looking statements, although not all forward-looking statements contain these words. These forward-looking statements involve significant risks, both known and unknown, uncertainties and other factors that may cause SMIC's actual performance, financial condition or results of operations to be materially different from those suggested by the forward-looking statements, including among others risks associated with the current global financial crisis, orders or judgments from pending litigation and financial stability in end markets.
Investors should consider the information contained in SMIC's filings with the U.S. Securities and Exchange Commission (SEC), including its Annual Report on Form 20-F filed with the SEC on June 22, 2009, especially in the "Risk Factors" and "Management's Discussion and Analysis of Financial Condition and Results of Operations" sections, and such other documents that SMIC may file with the SEC or SEHK from time to time, including on Form 6-K. Other unknown or unpredictable factors also could have material adverse effects on SMIC's future results, performance or achievements. In light of these risks, uncertainties, assumptions and factors, the forward-looking events discussed in this press release may not occur. You are cautioned not to place undue reliance on these forward-looking statements, which speak only as of the date stated, or if no date is stated, as of the date of this press release. Except as may be required by law, SMIC undertakes no obligation and does not intend to update any forward-looking statement, whether as a result of new information, future events or otherwise.
All trademarks are the property of their respective owners and are protected herein.
